The present invention generally relates to electrically conductive vias for three dimensional electronic and electromechanical device structures and particularly relates to a method for forming such vias in a substrate of such a device.
Electrically conductive vias are usually formed in a substrate material such as a silicon wafer to permit communication of signals between electronic devices such as transistors and the like located on opposite sides of the substrate. Such vias are occasionally referred to as through-wafer interconnections. Typically, the via is formed by initially forming an aperture extending through the substrate. As indicated in P. C. Andricacos et al. xe2x80x9cDamascene Copper Electroplating for Chip Interconnectionsxe2x80x9d IBM J. Res. Develop. 1998, Vol. 42, 567, the aperture is then filled with an electrically conductive material such as a metal. There are a variety of conventional deposition processes for filling an aperture with metal. Examples of such processes include the evaporation or sputtering of metal in vacuum, chemical vapor deposition (CVD), electroplating, or electroless deposition (ELD).
Evaporation or sputtering of metal in vacuum is a relatively simple technique involving placement of the substrate containing the apertures in a vacuum chamber. The entire surface of the substrate is then covered with a metal evaporated or sputtered from a source. Selective deposition of metal to selected areas of the substrate can be achieved by placing a mask between the source and the substrate. Such techniques are sometimes referred to as shadowed metallization. In an alternative technique, the mask is replaced by a patterned layer of resist covering the substrate save for the apertures to be filled. After metallization, surplus metal around the apertures is removed together with the underlying resist.
CVD also involves placing the substrate containing the apertures in a vacuum environment. In this technique, metallization is realized by decomposing a gaseous precursor compound of a metal injected inside the vacuum chamber. The gaseous compound decomposes and the metal, or an alloy thereof accumulates on the surface of the substrate. Selective metallization can be achieved through use of a gaseous precursor which reacts only with a specific material. By patterning such a material onto the substrate, deposition can be made selective.
Electroplating offers an alternative to the aforementioned techniques of metal deposition from vacuum. In electroplating, the substrate is immersed in an electroplating bath containing a metallic complex in solution. The metal content of the solution is deposited on the substrate by passing an electrical current through the substrate and the solution. It will be appreciated that the substrate should therefore be either conductive or otherwise made conductive. It will also be appreciated that the substrate should be compatible with the various chemicals forming the electroplating bath. In the event that the substrate is not electrically conductive, electroplating can be performed by initially applying a conductive layer by vacuum deposition for example. A resist patterned onto the surface of the substrate to be electroplated can localize metal deposition from solution to desired areas of the substrate. Electroplating can be performed at higher rates of deposition through use of a higher current density on the substrate. Electroplating can also be expedited by stirring the electroplating bath.
ELD is a similar process to that of electroplating. However, as indicated in G. O. Mallory, J. B. Haidu xe2x80x9cElectroless Plating: Fundamentals and Applicationsxe2x80x9d American Electroplaters and Surface Finishers Society, Orlando, Fla., USA, 1990, the substrate need not be conductive for ELD to work. In ELD, the surface of the substrate is immersed in a bath containing a metallic complex in solution. The metallic complex is reduced and deposited from the solution to the surface of the substrate as chemical species in the solution oxidize. It is not necessary to pass a current through the system. It will be appreciated then that ELD is attractive for covering insulating substrates with metals or alloys. ELD is promoted by placing a catalyst on the substrate to start or xe2x80x9cseedxe2x80x9d the deposition reaction. The reaction then typically continues in an autocatalytic manner. A patterned resist may be employed to keep the ELD of a metal localized to specific areas of the substrate.
Metal CVD is a relatively expensive process because it has a limited throughput and requires relatively complex and expensive equipment such as a vacuum chamber, pumps, valves. Additionally, metal CVD is unreliable at low temperatures, below 350 degrees centigrade, for example. Thus, metal CVD may be unsuitable for metallizing some heat-sensitive substrates. Furthermore, metal CVD exhibits a relatively slow deposition rate and is therefore unsuitable for filling vias having a diameter of the order of tens of micrometers.
Vacuum sputtering and deposition has similar disadvantages, again requiring relatively expensive equipment, and having limited deposition rates. Vacuum deposition involves pumping delays, thereby limiting throughput. Also, if the apertures are too narrow, they may be very difficult to fill with metal because of the shadowing effect of the walls of the apertures. Metal deposition from solution is suited to the filling of apertures with metals because such techniques are generally cheaper and faster. However, electroplating is not suited to all applications because, as indicated earlier, it requires at least a conductive layer on the substrate to start the electroplating process. This conductive or xe2x80x9cseedxe2x80x9d layer is typically deposited with one of the aforementioned techniques and thus introduces the associated disadvantages.
Filling vias with metal through ELD is difficult because the metal should be deposited relatively thickly so that vias are properly filled. However, relatively thick metal layers deposited by ELD tend to have relatively high internal mechanical stress and poor adhesion to the substrate. It is difficult to keep the metal deposited via ELD localized to the vias. Conventionally, the ELD catalyst is placed from solution onto the entire surface of the substrate. ELD then takes place everywhere both inside and outside the vias. Polishing of the substrate after deposition is then performed to remove surplus metal depositions. Post-deposition cleaning steps such as polishing are unsuitable for use in the fabrication of devices in which delicate microstructures are present because such structures are susceptible to damage by such actions. Coating the substrate with the ELD catalyst and then masking the catalyst outside the vias using a patterned resist is relatively expensive and difficult. Spin coating a resist onto the substrate having deep structures is also relatively difficult and requires relatively expensive equipment for performing the spin coating, alignment, exposure, development, and removal of the exposed resist.
Accordingly, it would be desirable to fill vias in a substrate with conductive material such as metal or alloy with better filling selectivity, at lower cost, and without demand for post-cleaning.
Thus, the present invention provides methods and apparatus for forming an interconnection in a substrate. An example embodiment of the method comprising: forming a via in the substrate; depositing a preconditioning layer on the substrate binding a catalyst layer to the preconditioning layer; depositing a conductive material on the catalyst layer by electro-less deposition to fill the via with the conductive material; and, selectively disabling deposition of the conductive material from coating surfaces of the substrate outside the via.
In advantageous embodiments of the present invention, an isolation layer is formed on the substrate prior to deposition of the preconditioning layer. The isolation preferably comprises an oxide of the substrate. Particularly advantageous embodiments of the present invention comprise hydrophilizing the substrate prior to deposition of the preconditioning layer.
In particularly advantageous embodiments of the present invention, the selective disabling comprises immersing the substrate in a processing solution and employing surface tension to prevent ingress of a processing solution into the via. The processing solution preferably comprises an aqueous solution. The aqueous solution may comprise an alkaline solution. Alternatively, the aqueous solution may comprise an oxidizing agent.
In an advantageous embodiment of the present invention, there is provided a method for selectively filling vias formed in a substrate. The filling of the vias is effected through electroless deposition of a metal or alloy without depositing excess of material outside the vias, thereby avoiding subsequent polishing steps necessary to remove surplus material outside the vias.
In an advantageous embodiment, vias in a substrate are filled by grafting from solution a relatively thin, homogeneous organic layer on the interior walls of the via and other surfaces of the substrate. The organic layer is then selectively removed from the surface of the substrate, but not from the interior of the vias. The removal is performed by plasma sputtering. Catalytic particles are then bound from solution to the residual organic layer remaining in the vias. The catalytic particles initiate the ELD of a metal inside the vias.